Resurrecting seL4’s WCET analysis
Authors
School of Computer Science and Engineering
UNSW,
Sydney 2052, Australia
Abstract
We report on our ongoing work to re-establish the WCET analysis of the latest version of the verified seL4 microkernel on the 64-bit RISC-V architecture. By modifying the Heptane analysis tool to include missing features and remove scalability problems, we can now perform the analysis on an unmodified kernel, currently using place-holder latencies and loop bounds. Establishing high-assurance loop bounds and infeasible-path refutations is in progress, as is determining sound instruction latencies.
BibTeX Entry
@inproceedings{Sillitoe_BGH_26,
address = {Lund, SE},
author = {Simon Sillitoe and Abdul Basit and Massimiliano Giacometti and Gernot Heiser},
booktitle = {Workshop on Operating System Platforms for Embedded Real-Time Applications (OSPERT)},
keywords = {worst-case execution time analysis, operating systems, microkernels, seL4},
month = jul,
numpages = {4},
paperurl = {https://trustworthy.systems/publications/papers/Sillitoe_BGH_26.pdf},
title = {Resurrecting {seL4}’s {WCET} Analysis},
year = {2026}
}
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